Signal processor for correcting and detecting errors

ABSTRACT

A signal processor performs error correction on data which has been subjected to predetermined signal processing, for each predetermined block unit, by an error correction block, in parallel with an operation of sequentially storing the data in a cache memory. Then, error detection is performed on the data for each predetermined block unit by a descrambling/error detection block, and the data is stored in a buffer memory. Based on the results of the error detection and the error correction, when there exists some error in the data, the data with the error, which is stored in the buffer memory, is read out to be subjected to error correction again. When there is no error, the data corresponding to one block and stored in the buffer memory is transmitted to a host computer without performing error correction again.

TECHNICAL FIELD

The present invention relates to a signal processor for detecting andcorrecting errors in data read from a recording medium.

BACKGROUND ART

In recent years, high quality and high speed are demanded of a DVD-ROM,which has become widespread as a digital memory, to increase thereliability of data read from a DVD disk. With the demand, a signalprocessor for correcting errors in the disk is required to have rapidprocessing means, and it is aimed at realization of high-speed dataprocessing.

A conventional CD-ROM signal processor performs error correction by apredetermined number of times. Further, the CD-ROM signal processorwrites inputted data in a buffer memory and, simultaneously, detectserrors in the data by using CRC (Cyclic Redundancy Check). Based on theresult of CRC, when the data is decided as “error-free data”, the signalprocessor reduces the predetermined number of error corrections.

In the case of DVD-ROM data, however, since inputted data is notpreviously subjected to error correction in contrast to the CD-ROM data,the error rate is higher in the DVD-ROM data than in the CD-ROM data.Therefore, when the DVD-ROM data is subjected to CRC, the result of CRCis, in most cases, that there are errors in the DVD-ROM data.

FIG. 6 is a block diagram illustrating the structure of a conventionalDVD-ROM signal processor.

In FIG. 6, a DVD-ROM signal processor 65 receives DVD-ROM digital signaldata (hereinafter referred to as “data”) which is read by an opticalpickup 61, and outputs the data after error correction to a hostcomputer 63. The DVD-ROM signal processor 65 is under control of acontrol microcomputer 62, and is connected with a buffer memory 64 whichstores data.

To be specific, the DVD-ROM signal processor 65 is provided with an FMTblock 651 for capturing the DVD-ROM data outputted from the opticalpickup 61, and storing it in the buffer memory 64; an error correctionblock 652 for correcting errors in the data stored in the buffer memory64; a descrambling block 653 for descrambling the scrambled data; anerror detection block 654 for detecting errors in the data after errorcorrection, which data is stored in the buffer memory 64; a hostinterface block 655 for transmitting error-free data to the hostcomputer, based on the result of the error detection by the errordetection block 654; and a memory interface block 656 for controllingthe processing between the DVD-ROM signal processor 65 and the buffermemory 64.

The operation of the conventional DVD-ROM signal processor soconstructed will be described with reference to FIGS. 4 and 6.

FIG. 4 is a diagram illustrating the data format constituting one ECCblock.

As shown in FIG. 4, the logical format of the DVD-ROM data outputtedfrom the optical pickup 61 is constituted with 182×208 bytes as one ECC(Error Correcting Code) block.

First of all, the data read by the optical pickup 61 forms one componentunit with 182 bytes as a C1 code word. The C1 code word is composed of172 bytes of user data and 10 bytes of C1 parity. One ECC block iscomposed of plural C1 code words and plural C2 code words, each C2 codeword comprising 208 bytes obtained by collecting one byte from each Clcode word. Each C2 code word is composed of 192 bytes of user data and16 bytes of C2 parity. The DVD-ROM data has been scrambled in advance.

In FIG. 6, the FMT block 651 converts the DVD-ROM serial data outputtedfrom the optical pickup 61 into parallel data (serial to parallelconversion), subjects the converted data to demodulation and syncdetection, and writes the parallel data in the buffer memory 64 throughthe memory interface block 656.

The error correction block 652 reads the DVD-ROM data written in thebuffer memory 64, through the memory interface block 656, performssyndrome calculation on the C1 code words and the C2 code words shown inFIG. 4, and calculates the error position and the error pattern by usingthe result of the syndrome calculation. Based on the result of thesyndrome calculation, the error correction block 652 terminates theerror correction when the data has no error. However, when the data hassome error, the error correction block 652 reads the error data storedin the buffer memory 64, through the memory interface block 656,performs error correction on the error data, and writes the correcteddata over the address of the error data stored in the buffer memory 64,through the memory interface block 656.

The descrambling block 653 reads the DVD-ROM data which has beensubjected to error correction and is stored in the buffer memory 64,through the memory interface block 656, descrambles the data accordingto a predetermined method, and writes the data in the buffer memory 64through the memory interface block 656.

The error detection block 654 reads the DVD-ROM data which has beendescrambled and is stored in the buffer memory 64, through the memoryinterface block 656, and detects errors in the read data by performing apredetermined calculation.

The host interface block 655 transmits, to the host computer 63, theDVD-ROM data which has been decided as “error-free data” in both of theerror correction block 652 and the error detection block 654.

Each of the above-mentioned blocks is constructed so as to operate at apredetermined timing according to an instruction from the controlmicrocomputer 62.

In the conventional DVD-ROM signal processor, however, when the DVD-ROMdata is subjected to error correction, the following operations areperformed on the buffer memory 64: writing of data from the FMT block651, reading and writing of data from the error correction block 652,reading and writing of data from the descrambling block 653, reading ofdata from the error detection block 654, and reading of data from thehost interface block 655. That is, since reading and writing of data areperformed frequently through the buffer memory 64, the memory band widthis pressed and, therefore, the signal processor cannot performhigh-speed access and higher-speed data processing.

The present invention is made to solve the above-described problem, andit is an object of the present invention to provide a signal processorwhich can reduce the number of memory accesses by reducing the number oferror corrections, thereby realizing higher-speed data processing.

SUMMARY OF THE INVENTION

A signal processor according to a first aspect of the present inventionis a signal processor for subjecting data read from a recording mediumto predetermined digital signal processing, and subjecting the data,which has been subjected to the predetermined digital signal processing,to error correction for each predetermined error correction block. Thissignal processor comprises: memory means for sequentially storing thedata which has been subjected to the predetermined digital signalprocessing; error correction means for subjecting the data, which hasbeen subjected to the predetermined digital signal processing, to errorcorrection for each predetermined error correction block;descrambling/error detection means for descrambling the data which hasbeen subjected to the error correction, and detecting errors in the dataafter the descrambling; and control means for transmitting error-freedata to a display unit when there is no error in the data which has beensubjected to the error detection.

In the signal processor so constructed, the number of data errorcorrections can be reduced, whereby reduced power consumption of thedevice itself can be achieved. Further, since the number of memoryaccesses to the memory means for error correction can be reduced, theaccess right to the memory means can be assigned to another block,whereby high-speed processing of the signal processor is realized.

According to the present invention, in the signal processor described inthe first aspect, the error correction means comprises: a syndromecalculator for calculating a syndrome of the data which has beensubjected to the predetermined digital signal processing; an errorposition/pattern calculator for calculating the error position and theerror pattern after the syndrome calculation; error correction resultholding means for holding information as to whether or not the datadetected by the error position/pattern calculator is error-correctable;data correction means for correcting errors in the data on the basis ofthe result of the syndrome calculation; and number-of-error-correctioncontrol means for controlling the number of error corrections.

In the signal processor so constructed, the time required for memoryaccess to the memory means can be reduced by reducing the number oferror corrections and, furthermore, speedup of data processing isachieved.

According to the present invention, in the signal processor described inthe first aspect, the descrambling/error detection means comprises:descrambling means for descrambling the data which has been corrected bythe error correction means; error detection means for detecting errorsin the descrambled data; and error detection result holding means forholding the result of the error detection as to whether there is anyerror in the data which has been subjected to the error detection.

In the signal processor so constructed, based on the result of errordetection, when there is no error, the data is transmitted to the hostcomputer without performing error correction again, whereby the numberof error corrections can be reduced. Accordingly, the power consumptionof the device itself can be reduced.

According to the present invention, in the signal processor described inthe first aspect, the data subjected to the predetermined digital signalprocessing is read from the memory means for each predetermined errorcorrection block, followed by error detection and error correction; whenthere is some error, the error is corrected by the error correctionmeans for each predetermined error correction block; when there is noerror, the data is transmitted to the display means for eachpredetermined error correction block.

In the signal processor so constructed, the time required for memoryaccess to the memory means can be reduced by terminating the second andmore error corrections or reducing the number of error corrections forthe data in each predetermined error correction block stored in thememory means, and further high-speed transmission of the data to thehost computer is achieved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating the structure of a DVD-ROM signalprocessor according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating the internal structure of anerror correction block according to a second embodiment of the presentinvention.

FIG. 3 is a block diagram illustrating the internal structure of adescrambling/error detection block according to a third embodiment ofthe present invention.

FIG. 4 is a diagram illustrating the data format constituting one ECCblock.

FIG. 5 is a timing chart of memory access in DVD-ROM signal processingaccording to a fourth embodiment.

FIG. 6 is a block diagram illustrating the structure of the conventionalDVD-ROM signal processor.

BEST MODE TO EXECUTE THE INVENTION

Embodiment 1

FIG. 1 is a block diagram illustrating the structure of a DVD-ROM signalprocessor according to a first embodiment of the present invention.

In FIG. 1, a DVD-ROM signal processor 15 receives DVD-ROM digital signaldata (hereinafter referred to as “data”) which is read by an opticalpickup 11, and outputs the data after error correction to a hostcomputer 13. The DVD-ROM signal processor 15 is controlled by a controlmicroprocessor (controller) 12, and the DVD-ROM signal processor 15 isconnected to a cache memory 16 for storing the data and to a buffermemory 14 for storing the data stored in the cache memory 16.

To be specific, the DVD-ROM signal processor 15 is provided with an FMTblock 151 for capturing the DVD-ROM data outputted from the opticalpickup 1; an error correction block 152 for correcting errors in thedata stored in the cache memory 16 and the buffer memory 14; adescrambling/error detection block 153 for descrambling the scrambleddata, and detecting errors in the descrambled data; an error detectionblock 154 for detecting errors in the data which has been subjected toerror correction and is stored in the buffer memory 14; a host interfaceblock 155 for transmitting error-free data to the host computer 13,based on the result of error detection by the error detection block 154;a memory interface block B 156 for controlling the processing betweenthe DVD-ROM signal processor 15 and the buffer memory 14; and a memoryinterface block A 157 for controlling the processing between the DVD-ROMsignal processor 15 and the cache memory 16.

The operation of the signal processor so constructed will be describedwith reference to FIGS. 1 and 4.

FIG. 4 is a diagram illustrating the data format constituting one ECCblock.

As shown in FIG. 4, the logical format of the DVD-ROM data outputtedfrom the optical pickup 11 is constituted with 182×208 bytes as one ECCblock.

First of all, the data read by the optical pickup 11 forms one componentunit with 182 bytes as a C1 code word. The C1 code word is composed of172 bytes of user data and 10 bytes of C1 parity. One ECC block iscomposed of plural C1 code words and plural C2 code words, each C2 codeword having 208 bytes obtained by collecting one byte from each C1 codeword. Each C2 code word is composed of 192 bytes of user data and 16bytes of C2 parity. The DVD-ROM data has been scrambled in advance.

Initially, with reference to FIG. 1, the DVD-ROM data outputted from theoptical pickup 11 is converted from serial data to parallel data (serialto parallel conversion) by the FMT block 151. The parallel data aresubjected to demodulation and sync detection, and one of the paralleldata is written in the cache memory through the memory 16 interfaceblock A 157. At the same time, another one of the parallel data istransmitted for each ECC block to the error correction block 152,wherein it is subjected to error correction. The data which has beensubjected to error correction by the error correction block 152 iswritten in the cache memory 16 through the memory interface block A 157.

Next, the data after error correction is read from the cache memory 16through the memory interface block A 157, and the scrambled data issubjected to descrambling and error correction by the descrambling/errordetection block 153, and the data is transmitted to the buffer memory 14through the memory interface block B 156. At this time, when thedescrambling/error detection block 153 detects some error in the data,error correction is carried out again by the error correction block 152.

The data which has been subjected to error correction by the errorcorrection block 152 is inputted to the error detection block 154through the buffer memory 14 and the memory interface block B 156,wherein error detection is carried out again. Based on the result of theerror detection, only the data decided as “error-free data” istransmitted to the host computer 13 through the host interface block155.

As described above, in the signal processor according to the firstembodiment, the DVD-ROM data inputted to the signal processor issubjected to error detection and error correction for every ECC block.When the data has some error, the data is subjected to error correctionfor every ECC block. When the data has no error, the data is transmittedto the host computer 13 for every ECC block. Therefore, although in theconventional example error correction is carried out by a predeterminednumber of times, such wasteful correction work is avoided, and thenumber of error corrections is reduced. Accordingly, it is possible toreduce the power consumption of the device itself. Further, since thenumber of memory accesses to the buffer memory 14 for error correctionis reduced, the access right to the buffer memory 14 can be assigned toanother block, whereby speedup of the signal processor is realized.

Embodiment 2

FIG. 2 is a block diagram illustrating the internal structure of anerror correction block according to a second embodiment of the presentinvention.

With reference to FIG. 2, an error correction block 152 is providedwith. a syndrome calculator 1521 for performing syndrome calculation; ascrambling circuit 1522 for scrambling descrambled data; an errorposition/pattern calculation block 1523 for calculating an errorposition in data and an error pattern on the basis of the result fromthe syndrome calculator 1521, and detecting data having uncorrectableerrors (hereinafter referred to as “error uncorrectable data”); an errorcorrection result holding circuit 1524 for holding information as towhether there is error uncorrectable data or not, which is detected inthe error position/pattern calculation block 1523; data correctioncircuit 1525 for correcting errors in the data according to the errorposition and the error pattern calculated from the syndrome by the errorposition/pattern calculation block 1523; and anumber-of-error-correction control circuit 1526 for controlling thenumber of error corrections.

The operation of the error correction block so constructed will bedescribed with reference to FIG. 2.

Initially, in the above-described first embodiment, the DVD-ROM datatransmitted to the error correction block 152 is inputted to thesyndrome calculator 1521 for each ECC block, wherein the data issubjected to syndrome calculation. At this time, if there is some errorat the point of time when 182 bytes of data equivalent to the C1 codeword have been inputted, the result of the syndrome calculation istransmitted to the error position/pattern calculation block 1523,wherein the error position and the error pattern are calculated.

In the error position/pattern calculation block 1523, it is detectedwhether or not there is any uncorrectable error, and the informationabout the presence or absence of uncorrectable error is stored in theerror correction result holding circuit 1524. The information about thepresence or absence of uncorrectable error, which is stored in the errorcorrection result holding circuit 1524, is output to thenumber-of-error-correction control circuit 1526.

On the other hand, the information about the error position and theerror pattern calculated in the error position/pattern calculation block1523 is transmitted to the data correction circuit 1525. The datacorrection circuit 1525 reads the data stored in the address indicatedby the error position from the cache memory 16 through the memoryinterface block A 157, and performs error correction by using the errorposition and the error pattern calculated by the error position/patterncalculation block 1523. The data which has been subjected to errorcorrection by the data correction circuit 1525 is written in the addressindicating the error position which is stored in the cache memory,through the memory interface block A 157.

The data which has been subjected to the first error correction in thisway is subjected to error detection in the descrambling/error detectionblock 153, and transmitted to the buffer memory 14 through the memoryinterface block B 156. At this time, when some error is detected in thedescrambling/error detection block 153, error correction is againcarried out in the error correction block 152. Hereinafter, this processwill be described in more detail.

In FIG. 2, the number-of-error-correction control circuit 1526 decideswhether there is any error in the data stored in the buffer memory 14,on the basis of the information from the error correction result holdingcircuit 1524 and the descrambling/error detection block 153 shown inFIG. 1. Based on the result of the detection, when there is no error,the number-of-error-correction control circuit 1526 outputs the statusof “free from error” to the control microcomputer 12. However, whenthere is some error in the data stored in the buffer memory 14, thenumber-of-error-correction control circuit 1526 outputs the status of“error” to the control microcomputer 12, and the syndrome calculator1521 performs syndrome calculation again.

The syndrome calculator 1521 reads the data with the error stored in thebuffer memory 14, through the memory interface block B 156. The readdata is initially subjected to scrambling by the scrambling circuit1522, and then converted to the data that can be subjected to syndromecalculation. The converted data is inputted to the syndrome calculator1521 for each ECC block, and subjected to syndrome calculation. If thereis some error at the point of time when 182 bytes of data equivalent tothe C1 code word or 208 bytes of data equivalent to the C2 code wordhave been inputted, the result of the syndrome calculation istransmitted to the error position/pattern calculation block 1523,wherein the error position and the error pattern are calculated.

Next, the information about the calculated error position and errorpattern is transmitted to the data correction circuit 1525. The datacorrection circuit 1525 reads the data in the address indicating theerror position from the buffer memory 14 through the memory interfaceblock B 156, and performs error correction by using the error positionand the error pattern calculated by the error position/patterncalculation block 1523. Then, the data which have been subjected toerror correction in the data error correction circuit 1525 is written inthe address indicating the error position of the data stored in thebuffer memory 14, through the memory interface block B 156.

As described above, in the signal processor according to the secondembodiment, syndrome calculation is performed on the data of each ECCblock unit, which is inputted to the error correction block 152, andthen error correction is performed on the data of each ECC block unitaccording to the result of the calculation. Therefore, the number oferror corrections can be reduced and, furthermore, the number of memoryaccesses to the memory means can be reduced. Accordingly, high-speeddata processing can be achieved.

Embodiment 3

FIG. 3 is a block diagram illustrating the internal structure of adescrambling/error detection block according to a third embodiment ofthe present invention.

In FIG. 3, a descrambling/error detection block 153 is provided with adescrambling circuit 1531 for descrambling scrambled data; an errordetection circuit 1532 for detecting errors in the descrambled data; andan error detection result holding circuit 1533 for holding the result oferror detection (presence or absence of error) by the error detectioncircuit 1532.

The operation of the descrambling/error detection block so constructedwill be described with reference to FIG. 3.

Initially, the data which has been subjected to error correction in theerror correction block 152 is inputted to the descrambling circuit 1531from the cache memory 16 through the memory interface block A 157, andthe data is descrambled according to a predetermined method. Thedescrambled data is transmitted to the error detection circuit 1532,wherein errors in the data are detected by a predetermined calculation.The data after the error detection is transmitted to the buffer memory14 through the memory interface block B 156. Further, information aboutthe result of the error detection by the error detection circuit 1532 islatched in the error detection result holding circuit 1533, and thenoutputted to the number-of-error-correction control circuit 1526 (seeFIG. 2) in the error correction block 152.

As described above, in the signal processor according to the thirdembodiment, the inputted data is descrambled and then subjected to errordetection. Based on the result of the error detection, when there is noerror, the data is transmitted to the host computer without performingdata correction again. Therefore, the number of error corrections can bereduced, resulting in reduced power consumption of the signal processor.

Embodiment 4

FIG. 5 is a timing chart of memory access of a DVD-ROM signal processoraccording to a fourth embodiment of the present invention.

First of all, each of codes shown in FIG. 5 will be described.

N˜N+3 denote block numbers of blocks when the data inputted to theDVD-ROM signal processor is subjected to error correction for each ECCblock.

Process 1 denotes the process from when the data inputted to the DVD-ROMsignal processor is inputted to the cache memory 16 and the errorcorrection block 152 through the FMT block 151 to when the first errorcorrection is carried out.

Process 2 denotes the process of performing the second and further errorcorrection in the error correction block 152 when the data has someerror in Process 1.

Process 3 denotes the process of transmitting error-free data to thehost computer 13 through the host interface block 155 when the data hasno error.

The operation of the DVD-ROM signal processor so constructed will bedescribed with respect to the timing of memory access, with reference toFIG. 5.

In FIG. 5, for example, the data corresponding to the Nth, (N+2)th, and(N+3)th blocks are constituted by the error-free or error correctable C1code word while the data corresponding to the (N+1)th block includes theerror uncorrectable C1 code word.

Initially, with respect to the data in the Nth, (N+2)th, and (N+3)thblocks, these data having no errors at the point of time when Process 1is ended are stored in the buffer memory 14. In this case, Process 1 isnot followed by Process 2 but followed by Process 3 wherein theerror-free data are transmitted for each ECC block to the host computer13.

On the other hand, with respect to the data in the (N+1)th block, sincethis data has an error at the point of time when Process 1 is ended,Process 1 is followed by Process 2 wherein the error data is corrected.Those blocks containing the data which are finally decided as“error-free error” are transmitted to the host computer 13 in Process 3.

As described above, according to the signal processor of this fourthembodiment, the DVD-ROM data inputted to the signal processor isprocessed for every ECC block from when capture of the data is startedto when the data is transmitted to the host computer 13. Therefore, inthe case where Process 1 is performed on the data corresponding to oneECC block and then Process 3 is performed without performing Process 2because there is no error, the access time inside the signal processorcan be reduced by one ECC block. Accordingly, high-speed transmission ofthe data to the host computer 13 is realized.

APPLICABILITY IN INDISTORY

As described above, the signal processor according to the presentinvention can reduce the number of memory accesses by reducing thenumber of error corrections to process data at higher speed. Especially,it is suitable as a signal processor for which high speed is demanded,such as a DVD-ROM.

1. A signal processor for subjecting data read from a recording mediumto predetermined digital signal processing, and subjecting the data,which has been subjected to the predetermined digital signal processing,to error correction for each predetermined error correction block, saidsignal processor comprising: a first memory operable to sequentiallystore the data which has been subjected to the predetermined digitalsignal processing; a descrambling/error detection unit operable toperform descrambling processing to the data which is stored in saidfirst memory and has been subjected to first error correction, andexecute error detection to the data after the descrambling processing; asecond memory operable to sequentially store the data which has beensubjected to the descrambling processing; an error correction unitoperable to perform the first error correction to the data stored insaid first memory and perform second error correction to the data insaid second memory if necessary; and a controller operable to transmiterror-free data which has been stored in said second memory to a hostcomputer, wherein, when said descrambling/error detection unit judgesthat there is an error in the data which has been subjected to thedescrambling processing, the data stored in said second memory are readout for each predetermined error correction block, and subjected toerror correction by said error correction unit, and when saiddescrambling/error detection unit judges that there is no error in thedata which has been subjected to the descrambling processing, said errorcorrection unit does not perform the second error correction, and saidcontroller transmits the data stored in said second memory to the hostcomputer.
 2. A signal processor as described in claim 1, wherein saiderror correction unit comprises: a syndrome calculator operable tocalculate syndrome of the data which has been subjected to thepredetermined digital signal processing; an error position/patterncalculator operable to calculate an error position and an error patternafter the syndrome calculation; an error correction result holding unitoperable to hold information as to whether or not the data detected bysaid error position/pattern calculator is error-correctable; a datacorrection unit operable to read erroneous data stored in said firstmemory, correct errors in the data, and store the data which has beensubjected to the error correction in said first memory based on theerror position and the error pattern calculated by said errorposition/pattern calculator; and a number-of-error-correction controlunit operable to control a number of error corrections.
 3. A signalprocessor as described in claim 1, wherein said descrambling/errordetection unit comprises: a first memory interface operable to read thedata stored in said first memory; a descrambling unit operable todescramble the data after the error correction which has been read fromsaid first memory; an error detection unit operable to detect errors inthe descramble data; a second memory interface operable to store thedescramble data in said second memory; and an error detection resultholding unit operable to hold a result of the error detection as towhether is any error in the data which has been subjected to the errordetection.